The present invention relates to a ferroelectric memory and a drive method therefor.
Ferroelectric memories using a ferroelectric as a capacitor have been partly put into practical use, in recent years, by virtue of their features such as nonvolatility and high-speed write/read capabilities.
When electric field is applied to a ferroelectric capacitor iteratively in positive and negative directions, the resulting polarization exhibits a hysteresis loop as shown in FIG. 6, where the axis of abscissas represents applied electric field and the axis of ordinates represents polarization value, showing that the ferroelectric capacitor can have two remanent polarization values of A and C states at an applied electric field of zero. Making these remanent values correspondent to a logical xe2x80x9c1xe2x80x9d and a logical xe2x80x9c0xe2x80x9d, respectively, allows two-valued logical data to be stored nonvolatile.
For reading data stored in this way, with a voltage applied to the ferroelectric capacitor connected to bit lines, electric charges generated by switching or non-switching of polarization according to stored data are outputted to the bit lines, by which a signal voltage is generated and thus the data reading is achieved. In this case, directions in which the polarization is switched or non-switched are correspondingly associated with the logical xe2x80x9c1xe2x80x9d and logical xe2x80x9c0xe2x80x9d, respectively. There can be conceived two types of methods for decision of signal voltage.
In a first type, a cell (2T2C) consisting of two ferroelectric capacitors and two transistors is provided to store one piece of logical data. Mutually opposite types of data are stored in the capacitors, where the capacitors are connected to a first bit line and a second bit line, respectively, and a signal voltage of the first bit line and a signal voltage of the second bit line are compared to each other to make a decision.
In a second type, a cell (1T1C) consisting of one ferroelectric capacitors and one transistor is used and a dummy cell for generating a reference voltage is provided, where a signal voltage generated on a first bit line and the reference voltage generated on a second bit line are compared to each other to make a decision. In this case, the reference voltage is desirably an intermediate voltage between the signal voltage of the logical xe2x80x9c1xe2x80x9d and the signal voltage of logical xe2x80x9c0xe2x80x9d.
For generation of the reference voltage, there have been developed various methods such as one disclosed in Japanese Patent Laid-Open Publications HEI 7-192476 and HEI 7-93978. In this method, two ferroelectric capacitors identical in construction to a memory cell are provided as a dummy cell to store a logical xe2x80x9c1xe2x80x9d and a logical xe2x80x9c0xe2x80x9d, and voltages resulting from reading the two capacitors are averaged, by which an intermediate voltage is generated. Another method is that, as shown in Japanese Patent Laid-Open Publication HEI 2-301093, the area of a ferroelectric capacitor constituting a dummy cell is made different from the area of a memory cell and a reference voltage is generated by utilizing this. Yet another method is that, as shown in Japanese Patent Laid-Open Publication HEI 5-114741, a capacitor using a normal paraelectric film is used as a dummy cell and an output voltage is increased by utilizing stored charges to provide an intermediate voltage between the signal voltage of a logical xe2x80x9c1xe2x80x9d and the signal voltage of a logical xe2x80x9c0xe2x80x9d.
The 2T2C type memory cell, in which two transistors and two capacitors are needed for one piece of stored data, is unsuitable for high integration. Also, the 1T1C type memory cell, in which the read margin is one half that of the 2T2C type memory cell, is required to generate signal voltages and a reference voltage with high precision.
However, in the method disclosed in Japanese Patent Laid-Open Publication HEI 2-301093, in which a dummy cell having a capacitor different in electrode area from a memory cell is used, the reference voltage is determined according to a capacitance value at either switching or non-switching of polarization, thus making it difficult to generate an intermediate voltage with high precision. Further, because of differences in ferroelectric capacitor area between data cells and dummy cells, the setting of process conditions becomes difficult due to variations in capacitance characteristics or the like. The case is the same, as to such a problem, also with the method disclosed in Japanese Patent Laid-Open Publication HEI 5-114741.
Furthermore, in the method using two capacitors as a dummy cell as disclosed in Japanese Patent Laid-Open Publications HEI 7-192476 and HEI 7-93978, although it is theoretically possible to generate an intermediate voltage, the dummy cell needs to generate a reference voltage each time data cells connected to the same cell array are read. As a result of this, the number of operations required for the dummy cell becomes quite larger than that required for the data cell. Since a ferroelectric undergoes deteriorations, called imprint and fatigue, that depend on the number of reads, only the dummy cells that undergo larger numbers of reads than data cells would further deteriorate, making it impossible to correctly generate an intermediate voltage.
Therefore, an object of the present invention is to provide a ferroelectric memory being capable of suppressing deterioration of dummy cells undergo larger number of reads than data cells and generating an intermediate voltage correctly.
In order to achieve the above object, there is provided a ferroelectric memory comprising:
a memory cell array having at least three or more memory cells (FSk) each of which comprises a ferroelectric capacitor (FCk) for storing a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d depending on a direction of spontaneous polarization, and a first transistor (TAk) and a second transistor (TBk) connected in parallel to one electrode of the ferroelectric capacitor (FCk);
a first bit line (BLA) to which the ferroelectric capacitors (FCk) of the memory cells are connected in parallel via the first transistors (TAk);
a second bit line (BLB) to which the ferroelectric capacitors (FCk) of a plurality of memory cells are connected via the second transistors (TBk); and
a decision device for comparing a voltage of the first bit line (BLA) and a voltage of the second bit line (BLB) to each other to decide whether data is a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d.